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Welcome to the documentation for OpenCEHardware’s ScaleNPU hardware module. This resource provides a comprehensive guide to understanding and working with the ScaleNPU block, detailing its current capabilities, configurations, and design specifications.

To help you get the most out of this documentation, we've organized it into the following sections:

  • Revisions: Documentation on previous versions and changes made.
  • Document Conventions: Definitions and abbreviations used in the document.
  • Introduction: General description of the ScaleNPU and its features.
  • Block Diagram: Visual representation of the ScaleNPU microarchitecture.
  • Configuration: Information about parameters, typedefs, and RTL interfaces.
  • Protocols: Details of communication and operation protocols.
  • Memory Map: Distribution of memory and resource allocation.
  • Registers: Description of the registers used in the system.
  • Clock Domains: Information about clocks and their management in the system.
  • Reset Domains: Information about reset mechanisms and their domains.
  • Interrupts: Management and handling of interrupts in the system.
  • Arbitration: Arbitration mechanisms for access to shared resources.
  • Debugging: Techniques and tools for system debugging.
  • Synthesis: Summary and results of the design synthesis.
  • Verification: Test environments, verification and testbenches applied to the system.
  • Microarquitecture Preamble: Overview of the teorical principles, data flow, and design rationale behind the ScaleNPU’s microarchitecture.
  • Microarchitecture:
    • MAC: Multiply-accumulate unit for core computational operations.
    • FIFO: First-In-First-Out buffers for data handling and synchronization.
    • Gatekeeper: Access control and resource management.
    • Accumulator: Accumulation of computation results.
    • Activation: Activation function application for inference.
    • Systolic Array: Systolic data flow for matrix operations.
    • Inference: Management of inference processes.
    • Memory Ordering: Ordering and management of memory requests.
    • Memory Interface: Interface for accessing external memory resources.
    • Executive: Control and orchestration of the ScaleNPU’s operations.

Acknowledgements

Please check the References section for more information.