Executive
Description
The hs_npu_executive
module serves as the interface between the PeakRDL (autogenerated) CSR module and the memory ordering unit, managing control signals and configurations for the ScaleNPU system. It processes CSR values to configure layer parameters, matrix dimensions, and memory addresses. Additionally, it manages control flags for reusing inputs, applying bias, and selecting activation functions, along with interrupt signaling. This submodule coordinates between the CSR interface and memory ordering.
This module also handles error codes and performs basic checks on the parameters passed in the CSRs, currently validating that the input size does not exceed the maximum input and output buffer size.
Note
If more error/exit codes are to be added, this module and the CSR module are the appropriate places to do so. For example, the memory interface always assumes memory does not fail. This module could connect to the memory interface and link to AXI failure signals so that, in case of a memory error, it is reported to the CPU.
I/O Table
Input Table
Input Name | Direction | Type | Description |
---|---|---|---|
clk |
Input | logic |
Clock signal for synchronization. |
rst_n |
Input | logic |
Active-low reset signal. |
hwif_out |
Input | hs_npu_ctrlstatus_regs_pkg::hs_npu_ctrlstatus_regs__out_t |
CSR output values for configuration and control flags. |
memory_ordering_ready_i |
Input | logic |
Indicates readiness from the memory ordering unit for new commands. |
finished |
Input | logic |
Signal indicating completion of the current task. |
Output Table
Output Name | Direction | Type | Description |
---|---|---|---|
hwif_in |
Output | hs_npu_ctrlstatus_regs_pkg::hs_npu_ctrlstatus_regs__in_t |
CSR input signals to update internal states and trigger interrupts. |
irq |
Output | logic |
Interrupt request signal for the CPU upon task completion. |
memory_ordering_valid_o |
Output | logic |
Valid signal indicating new command for memory ordering unit. |
num_input_rows_out |
Output | uword |
Number of rows in the input matrix from the CSR. |
num_input_columns_out |
Output | uword |
Number of columns in the input matrix from the CSR. |
num_weight_rows_out |
Output | uword |
Number of rows in the weight matrix from the CSR. |
num_weight_columns_out |
Output | uword |
Number of columns in the weight matrix from the CSR. |
reuse_inputs_out |
Output | logic |
Flag to reuse input data across computations. |
reuse_weights_out |
Output | logic |
Flag to reuse weights across computations. |
save_outputs_out |
Output | logic |
Flag to save computation outputs. |
use_bias_out |
Output | logic |
Enables bias in the computation. |
use_sum_out |
Output | logic |
Enables sum accumulation in the computation. |
shift_amount_out |
Output | uword |
Shift amount for adjusting results post-computation. |
activation_select_out |
Output | logic |
Activation function selection for computation. |
base_address_out |
Output | uword |
Base memory address for data access. |
result_address_out |
Output | uword |
Memory address for storing results. |
Submodule Diagram
The diagram is trivial.
Related Files
File Name | Description |
---|---|
hs_npu_executive | Top module |
hs_npu_ctrlstatus_regs | Defines CSR structure and types used by the module. |
Note
The actual .sv of the CSRs is autogenerated by PeakRDL. Look within the \regblock directory inside \build to find it.