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Registers

This section lists all registers in the ScaleNPU block, which include only the Control and Status Registers (CSRs).

CSRs (Configuration/Status Registers)

The Control and Status Registers (CSRs) in the ScaleNPU provide a direct interface for the CPU to configure, monitor, and control NPU operations. Through these registers, the CPU can set up tasks by specifying parameters such as matrix dimensions, memory addresses, and operational modes, and initiate processing tasks for a single layer calculation. The CSRs also allow the CPU to monitor the NPU's status, check task completion, detect errors, and manage task-related interrupts.

The following CSR sections were auto-generated by PeakRDL using the .rdl file as the source.

hs_npu_ctrlstatus_regs address map

  • Absolute Address: 0x0
  • Base Offset: 0x0
  • Size: 0x48

Control and status registers for configuring the Scale NPU.

Offset Identifier Name
0x00 NPUINFO Accelerator Information
0x08 DIMS Matrix Dimensions
0x18 CTRL Layer Control Flags
0x34 MEMADDRS Memory Addresses
0x3C MAINCTRL Main control registers

NPUINFO register file

  • Absolute Address: 0x0
  • Base Offset: 0x0
  • Size: 0x8

Contains registers that provide architecture and implementation details of the accelerator.

Offset Identifier Name
0x0 ARCHID Architecture ID
0x4 IMPID Implementation ID

ARCHID register

  • Absolute Address: 0x0
  • Base Offset: 0x0
  • Size: 0x4

Encodes the base microarchitecture of the accelerator.

Bits Identifier Access Reset Name
31:0 ID r 0xB00B —

IMPID register

  • Absolute Address: 0x4
  • Base Offset: 0x4
  • Size: 0x4

Provides a unique encoding of the version of the accelerator implementation.

Bits Identifier Access Reset Name
31:0 ID r 0x100 —

DIMS register file

  • Absolute Address: 0x8
  • Base Offset: 0x8
  • Size: 0x10

Registers for specifying the dimensions of input and weight matrices.

Offset Identifier Name
0x0 INROWS Input Matrix Rows
0x4 INCOLS Input Matrix Columns
0x8 WGHTROWS Weight Matrix Rows
0xC WGHTCOLS Weight Matrix Columns

INROWS register

  • Absolute Address: 0x8
  • Base Offset: 0x0
  • Size: 0x4

Number of rows in the input matrix.

Bits Identifier Access Reset Name
7:0 ROWS rw — —

INCOLS register

  • Absolute Address: 0xC
  • Base Offset: 0x4
  • Size: 0x4

Number of columns in the input matrix.

Bits Identifier Access Reset Name
7:0 COLS rw — —

WGHTROWS register

  • Absolute Address: 0x10
  • Base Offset: 0x8
  • Size: 0x4

Number of rows in the weight matrix.

Bits Identifier Access Reset Name
7:0 ROWS rw — —

WGHTCOLS register

  • Absolute Address: 0x14
  • Base Offset: 0xC
  • Size: 0x4

Number of columns in the weight matrix.

Bits Identifier Access Reset Name
7:0 COLS rw — —

CTRL register file

  • Absolute Address: 0x18
  • Base Offset: 0x18
  • Size: 0x1C

Registers for configuring control signals of a particular layer calculation.

Offset Identifier Name
0x00 REINPUTS Results as Input
0x04 REWEIGHTS Reuse Weights
0x08 SAVEOUT Save Output
0x0C USEBIAS Use Bias
0x10 USESUMM Use Summatory
0x14 SHIFTAMT Shift Amount
0x18 ACTFN Activation Function Selection

REINPUTS register

  • Absolute Address: 0x18
  • Base Offset: 0x0
  • Size: 0x4

Flag to use the results of the previous layer calculation as the input matrix.

Bits Identifier Access Reset Name
0 REUSE rw — —

REWEIGHTS register

  • Absolute Address: 0x1C
  • Base Offset: 0x4
  • Size: 0x4

Flag to reuse the weights of the previous layer computation.

Bits Identifier Access Reset Name
0 REUSE rw — —

SAVEOUT register

  • Absolute Address: 0x20
  • Base Offset: 0x8
  • Size: 0x4

Flag to save the output after layer computation.

Bits Identifier Access Reset Name
0 SAVE rw — —

USEBIAS register

  • Absolute Address: 0x24
  • Base Offset: 0xC
  • Size: 0x4

Flag to enable bias addition during computation.

Bits Identifier Access Reset Name
0 USE rw — —

USESUMM register

  • Absolute Address: 0x28
  • Base Offset: 0x10
  • Size: 0x4

Flag to use summatory values for the results.

Bits Identifier Access Reset Name
0 USE rw — —

SHIFTAMT register

  • Absolute Address: 0x2C
  • Base Offset: 0x14
  • Size: 0x4

Amount of shift for quantization.

Bits Identifier Access Reset Name
7:0 AMOUNT rw — —

ACTFN register

  • Absolute Address: 0x30
  • Base Offset: 0x18
  • Size: 0x4

Selects the activation function to apply (0: None, 1: ReLU).

Bits Identifier Access Reset Name
0 SELECT rw — —

MEMADDRS register file

  • Absolute Address: 0x34
  • Base Offset: 0x34
  • Size: 0x8

Registers for setting the base memory address for matrix data and the result address.

Offset Identifier Name
0x0 BASE Base Memory Address
0x4 RESULT Result Memory Address

BASE register

  • Absolute Address: 0x34
  • Base Offset: 0x0
  • Size: 0x4

Base address in memory for matrix data.

Bits Identifier Access Reset Name
31:0 ADDR rw — —

RESULT register

  • Absolute Address: 0x38
  • Base Offset: 0x4
  • Size: 0x4

Memory address for storing the result.

Bits Identifier Access Reset Name
31:0 ADDR rw — —

MAINCTRL register file

  • Absolute Address: 0x3C
  • Base Offset: 0x3C
  • Size: 0xC

Control registers to signal the start and end of an operation.

Offset Identifier Name
0x0 INIT Initialize
0x4 IRQ Interrupt
0x8 EXITCODE Exit code

INIT register

  • Absolute Address: 0x3C
  • Base Offset: 0x0
  • Size: 0x4

Signals the NPU to start operation with the current register data.

Bits Identifier Access Reset Name
0 VALUE w1 — —

IRQ register

  • Absolute Address: 0x40
  • Base Offset: 0x4
  • Size: 0x4

Interrupt signals cominng from the NPU. Signals the NPU has finished

Bits Identifier Access Reset Name
0 FINISHED rw, woclr — —

EXITCODE register

  • Absolute Address: 0x44
  • Base Offset: 0x8
  • Size: 0x4

Exit code produced by the NPU once the operation finishes. UNUSED = 00, SUCCESS = 01, MEM_ERR = 10, CPU_ERR = 11

Bits Identifier Access Reset Name
1:0 CODE r — —