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Welcome to the documentation for H-SCALE, the heterogeneous hardware project that encompasses both the ScaleNPU and ScaleCore-V modules. This resource provides a comprehensive guide to understanding and working with the various components of the H-SCALE project, detailing their current capabilities, configurations, and design specifications.

To help you get the most out of this documentation, we've organized it into the following sections:

  • Revisions: Documentation on previous versions and changes made.
  • Document Conventions: Definitions and abbreviations used in the document.
  • Introduction: General description of the block and its features.
  • Block Diagram: Visual representation of the block's microarchitecture.
  • Configuration: Information about parameters, typedefs, and RTL interfaces.
  • Protocols: Details of communication and operation protocols.
  • Memory Map: Distribution of memory and resource allocation.
  • Registers: Description of the registers used in the system.
  • Clock Domains: Information about clocks and their management in the system.
  • Reset Domains: Information about reset mechanisms and their domains.
  • Interrupts: Management and handling of interrupts in the system.
  • Arbitration: Arbitration mechanisms for access to shared resources.
  • Debugging: Techniques and tools for system debugging.
  • Synthesis: Summary and results of the design synthesis.
  • Verification: Test environments, verification and testbenches applied to the system.
  • Cores: Computational cores of the system.