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Welcome to the documentation for OpenCEHardware’s ScaleCore-V hardware module. This resource provides a comprehensive guide to understanding and working with the ScaleCore-V block, detailing its current capabilities, configurations, and design specifications.

To help you get the most out of this documentation, we've organized it into the following sections:

  • Revisions: History of updates and changes made to the ScaleCore-V module.
  • Document Conventions: Definitions, abbreviations, and standards used throughout the document.
  • Introduction: Overview of the ScaleCore-V module and its key features.
  • Block Diagram: Visual representation of the ScaleCore-V microarchitecture.
  • Configuration: Information about module parameters, typedefs, and RTL interfaces.
  • Protocols: Details on communication and operational protocols within ScaleCore-V.
  • Memory Map: Structure and allocation of memory resources in the ScaleCore-V.
  • Registers: Description of registers utilized in the ScaleCore-V system.
  • Clock Domains: Clock structure and domain management within ScaleCore-V.
  • Reset Domains: Information on reset mechanisms and domain organization.
  • Interrupts: Management and handling of interrupts within the ScaleCore-V module.
  • Arbitration: Methods for arbitration and shared resource access control.
  • Debugging: Techniques and tools for debugging the ScaleCore-V system.
  • Synthesis: Overview of design synthesis and performance results.
  • Verification: Verification strategies, environments, and testbenches used with ScaleCore-V. Here's the updated Microarchitecture section with the correct sub-modules:
  • Microarchitecture:
    • Fetch: Fetching and instruction retrieval mechanism.
    • Decode: Instruction decoding and preparation for execution.
    • Issue: Issuing instructions to relevant execution units.
    • ALU: Arithmetic and logical operations performed by the ALU.
    • Branch: Branch prediction and handling mechanisms.
    • Foo: Additional unit for extra operations.
    • Memory: Memory management and access control.
    • Control-Status: Control and status register management.
    • Commit: Commit process for finalized instructions.
    • Skid-Buffer: Buffering for pipeline delays and instruction stalls.
    • FIFO: First-In-First-Out buffer management for data handling.

Acknowledgements

Please check the References section for more information.